Novel loop architectures for enhancing linearity and resolution of analog-to-digital converters

This paper proposes three mixed (analog and digital) loop architectures which involve an analog-to-digital converter and enhance its linearity and its resolution. Their benefits are discussed with mathematical models and high-level simulations (the ADC inserted in the loops is then a passive sigma-delta structure). One of the loop topologies is particularly highlighted: it is ideally able to enhance resolution by 5 bits without damaging bandwidth. The only added analog element is an active differential low-pass filter. The other operators are fully digital: a predictor and some models of the analog parts. The effect of some defaults, such as mismatch and common mode, is illustrated by high-level simulations. The needed accuracy for the digital parameters is evaluated to 16 bits. The test of a prototype realized in a 0.358m CMOS technology validates the principle and demonstrates that the critical element of the structure is the active differential filter

A Sigma-Delta Converter with Adjustable Tradeoff between Resolution and Consumption

International audienceThis paper proposes an analog-to-digital converter with two working modes. In the first mode, the system is a sigma-delta passive converter: the analog modulator uses a passive switched-capacitor low-pass filter and the only active element is the comparator. The consumption is low and the resolution is moderate (9 bits). In the second mode, the expected resolution is 15 bits. For that, the passive sigma-delta modulator is put in a loop with a low-pass amplifier and some digital processing elements. The principle of this two-mode system is validated by functional simulations and by the test of a circuit realized in a 0.35μm CMOS technology

Un convertisseur sigma-delta passif-actif bi-modes

National audienceCet article présente un convertisseur analogique-numérique possédant deux modes de fonctionnement. Le premier mode se caractérise par une très faible consommation, associée à une faible résolution (9 bits). Dans le second mode, la résolution est accrue de 6 bits en théorie ; en contrepartie, la consommation augmente. En mode « faible consommation », le système est un convertisseur sigma-delta passif c'est-à-dire dont le modulateur utilise un filtre passe-bas passif, le seul élément actif étant le comparateur. En mode « haute résolution », le modulateur passif est positionné dans une boucle comprenant notamment un filtre passe-bas actif. Le principe de cette topologie bi-modes a été validé par des simulations au niveau fonctionnel et par le test d'un circuit prototype réalisé en technologie CMOS 0.350m

Analyse et compensation des imperfections des blocs élémentaires d'un convertisseur modulateur sigma-delta à temps continu en technologie AsGa

La conception des modulateurs sigma-delta passe bande à temps continu, dédiés à la conversion analogique-numérique de signaux radiofréquences, se heurte à de nombreuses difficultés car les technologies sont utilisées aux limites de leurs possibilités. Les imperfections résultant de la réalisation au niveau circuit des blocs fonctionnels idéaux sont susceptibles de dégrader considérablement les performances. Cet article analyse l'influence de deux imperfections (les termes passe-bas des résonateurs à temps continus et la bande passante du sommateur) et propose des solutions de compensation génériques. A titre d'illustration, la démarche est mise en oeuvre pour la conception d'un modulateur d'ordre 6 prévu pour fonctionner à une fréquence de sur-échantillonnage de 3 GHz, pour une fréquence centrale de 750 MHz et une largeur de bande d'environ 10 MHz. Des résultats obtenus par simulation au niveau transistor en technologie AsGa HEMT 0.2, sont présentés

Central Frequency Tuning Considerations for Gm-C Resonators in GaAs Technology

International audienceThe ability of adjustment of the central frequency of a Gm-C resonator in GaAs technology is discussed. First, it is shown that whatever the technology the wanted quality factor can be reached through an appropriate sizing of the transconductance values, with adding an external feedback capacitor in the transconductance amplifiers. Then, it is demonstrated that the adjustment of the central frequency must be made preferentially by a specifical transconductance. Finally, because in GaAs technologies varying the transconductance values leads to current offsets which could damage the performances, the maximal allowed current offsets are determined. To illustrate these considerations, simulation at transistor level of a proposed structure in GaAs P-HEMT 0.2 ¹m with integrated feedback capacitors is presented and demonstrates a tunable central frequency from 750 to 810 MHz

DESIGN OF A 3 GHz 6TH ORDER DELTA-SIGMA MODULATOR IN A 0.2 μm GaAs TECHNOLOGY

International audienceThis paper presents the design of a monobit 6th order delta-sigma modulator in a GaAs 0.2 μm technology. The central frequency is 750 MHz and the sampling frequency is 3 GHz. The reached resolution is 10.5 bits over a 10 MHz bandwith. The modulator operates from ± 5 V power supplies and consumes 5.7 W. Each block of the modulator is presented at transistor level. Two drawbacks are pointed out: low pass terms of Gm-LC resonators and the lowpass characteristic of the adder. Two solutions are proposed. Finally, simulation results of the complete modulator are given